COLLECTIVE COMMUNICATION-AWARE HIGH PERFORMANCE NETWORK-ON-CHIP ARCHITECTURES FOR BIG DATA PROCESSING
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In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and highly scalable platform suitable for both data- and compute-intensive applications. The performance of a manycore architecture is highly dependent on the capabilities of its communication backbone, namely the Network on-chip (NoC). An efficient NoC designed for a manycore platform must align the connectivity of the NoC with the application’s on-chip traffic patterns. Analysis on the inter-core traffic patterns exhibited by various Big Data applications reveal irregular memory access behaviors that give rise to long-range on-chip communication requirements. In addition to the irregular memory access patterns, many of the modern applications also necessitate dense collective communication capabilities among the on-chip nodes. Under collective communication, either a single source node transmits data to all the other nodes in the system (one-to-all) or all the nodes in the system communicate with a single destination node (all-to-one). Wireless NoC is an emerging paradigm to design high bandwidth and energy efficient communication backbone for manycore chips. Previous works show that the wireless links can establish low-latency data-transfers even between physically distant on-chip nodes. In addition, with its inherent broadcast capability, the on-chip wireless links are highly suited to perform efficient collective-communication. Thus, employing on-chip wireless links one can design efficient communication infrastructures for manycore platforms running high performance Big Data processing. This dissertation focuses on designing a hybrid (wireline + wireless) network-on-chip architecture (called WiNoC) capable of low-latency collective communication. First, we leverage the knowledge gained from studying small-world graphs to design low hop count WiNoC topologies. Next, we augment the WiNoC with suitable data-transfer mechanisms to ensure a congestion-free high performance NoC. On overall, this work indicates on-chip communication challenges arise from manycore Big Data processing and proposes a wireless-enabled high performance and energy efficient NoC capable of addressing these challenges.