Towards Energy Efficient And Reliable 3D Manycore Chip Enabled By Machine Learning
MetadataShow full item record
As the demand for high performance and energy efficient computation has increased significantly, manycore chip architectures have emerged as a mainstream solution paradigm. A three-dimensional Network-on-Chip (3D NoC) that takes the advantages of amalgamation of two revolutionary technologies namely the NoC and 3D integration, improves the performance of manycore chip significantly. Existing 3D NoC architectures predominantly follow straightforward extension of regular 2D NoCs and suffer from multi-hop communications. In this context, we propose the design of 3D small-world NoC (3D SWNoC) architecture to overcome the challenges of mesh-based architectures and improve the performance of the chip. In addition, the performance of 3D SWNoC mainly depends on the placement of cores and links. This is an instance of combinatorial optimization problem, which is computationally intractable and needs intelligent exploration of design space to reach physically plausible and near-optimal designs. We adapt a machine learning-based approach to overcome these computational challenges and design an efficient and robust NoC architecture while ensuring significant reduction in convergence time. The anticipated performance gain of 3D NoCs degrades in the presence of TSV failures due to fabrication limitations and workload induced stress. We analyze the reliability concerns associated with 3D ICs. We propose several mitigation techniques to counteract TSV failures, which includes VFI-based power management methodology, spare TSV allocation technique, and adaptive routing strategy. We carry out extensive experiments to characterize their performance to improve both reliability and lifetime of 3D NoCs. Recently, monolithic 3D (M3D) integration has been proposed as an alternative to TSV-based 3D integration for designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of monolithic inter-tier vias (MIVs) offer high density integration, flexibility of partitioning logic blocks across multiple tiers resulting in significant reduction of the total wire-length. In this work, we explore the design space of M3D-enabled small-world NoC architectures and present a comparative performance evaluation with TSV-based counterparts. Finally, we summarize our contributions and outline some promising directions for future work based on the findings of this work. Future work includes incorporating machine learning approaches for on-chip security analysis and development of online mitigation techniques against external attacks.