NETWORK-ON-CHIP ENABLED MANYCORE ARCHITECTURES FOR CYBER-PHYSICAL SYSTEM
Predicting and controlling is the long-cherished goal of human. Among the various framework of prediction and control, the Cyber-Physical System (CPS) is a promising approach and grows fast in both academic and industry field in recent years. CPS refers to a new generation of system with integrated computation, networking, and physical processes that can interact with humans to achieve stability, performance, reliability and robustness in dealing with physical systems. The advance of peripheral techniques has activated many researches of involving CPS in mechanical, chemical, biomedical and many other fields. In turn, the widely adoption of CPS has created more complex systems and algorithms, which calls for a more powerful and efficient hardware platform to handle with. Towards this requirement, manycore architecture is a very promising candidate for future CPS platform. Manycore architectures offer a low power and highly scalable platform suitable for both data- and compute-intensive applications. The performance of a manycore architecture is highly dependent on the capabilities of its communication backbone, namely the Network on-chip (NoC). An efficient NoC designed for a manycore platform must align the connectivity of the NoC with the application’s on-chip traffic patterns, which makes the software-hardware co-design necessary for high efficiency CPS platform. Wireless NoC is an emerging paradigm to design high bandwidth and energy efficient communication backbone for manycore chips. Previous works show that the wireless links can establish low-latency data-transfers even between physically distant on-chip nodes. Thus, employing on-chip wireless links one can design efficient communication infrastructures for manycore platforms running high performance CPS application. This dissertation focuses on design methodologies of CPS applications specific hybrid (wireline + wireless) network-on-chip architecture (called WiNoC). We leverage the knowledge gained from CPS application analysis and efficient topology optimization algorithm in designing high performance WiNoC topologies. In addition, we augment the WiNoC with dynamic characteristics to fit the communication requirement. In addition, we explore the scalability of our WiNoC architecture. On overall, this work indicates the challenges of CPS application specific manycore platforms design and proposes the design and optimization methods for wireless-enabled high performance and energy efficient NoC capable of handling CPS applications.