DESIGN AND OPTIMIZATION OF A LOW POWER RADIO FOR WPAN/BAN
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This thesis investigates the design of high data rate and low-power wireless-links for RF applications of Wireless Private Area Network (WPAN)/Body Area Network (BAN). The primary goal is to identify suitable architectures and circuits, optimization algorithms and implementations of high energy efficient wireless-links. Three key enabling technologies are investigated in this work: high energy efficient circuit design, implementation algorithms and integrated circuit fabrication. Opportunities for convergence in these three areas are considered, and low power radio architectures are presented as a principal means to exploit this anticipated convergence. In the first part, a wireless biotelemetry system operates in vivo, which requires low power consumption for long-lasting operation, high output power for long transferable distance, and high throughput for incorporating many recording electrodes and transmitting raw brain signals. An implantable 2.4-GHz on-off keying (OOK) transmitter with high throughput and high energy efficiency for wireless biotelemetry systems has been designed in a 0.18-µm CMOS process. To balance power consumption and output power, a complementary voltage-controlled oscillator for the proposed transmitter is employed. Power consumption of the transmitter is reduced by switching the oscillator on and off to generate an OOK modulated signal. The transient delay for the transmitter is derived and applied to implement a high throughput transmitter. Rat skin-mimic emulating the implant environment such as electrical properties of the skin is used to measure the proposed transmitter in vitro. To transmit 136 Mb/s of OOK data, the transmitter consumes 3 mW of dc power and generates an output power of 14 dBm. The transmitter achieves energy efficiency of 22 pJ/bit with an associated bit error rate of 1.7 × 10-3 without using an error correction scheme. In the second part, the low power frequency synthesis is the most important building block to implement a low power radio because it is one of the most power hungry circuits on the transceiver. This thesis presents a voltage controlled oscillator (VCO) and a time-amplifier in order to generate the low power frequency synthesis. A power-minimized LC VCO with switched biasing and triode-region MOSFETs has been designed using a 0.18-µm CMOS process. The design strategy for an LC VCO suggested an inductance selection scheme to accommodate the trade-off between power consumption and phase noise. The Figure-Of-Merit with the normalized area of the proposed VCO is -198.2 dB, which is the lowest among the latest state-of-the-art sub-1mW VCOs. A high resolution time-amplifier has been simulated based on a 0.18-µm CMOS process. Based on the proposed low power VCO and the proposed high resolution time-amplifier with the variable delay buffer, the low power frequency synthesis can be implemented near future.