LOW POWER LOW NOISE BODY-ENABLED PHASE LOCKED LOOP FOR WIRELINE AND WIRELESS TRANSCEIVERS
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To meet peoplefs needs in social connection, health care and all areas of our IT-fused society, wireline and wireless communication technologies have been the driving forces of human innovation. In communication systems, Phase Locked Loop (PLL) has played an ever-increasing role in that the phase noise of PLL is dominant of the random jitter (RJ), which may degrade the bit error rate (BER) a lot. While significant research work has been conducted to improve the PLL phase noise, the desire for low power consumption puts more challenges in the design of high performance PLL. This dissertation exploits body-enabled techniques, which are enabled by the triple-well process, in the design low power PLL. The novel charge pump PLL will be presented aiming at low voltage, low power, and low phase noise at high carrier frequencies. Significant work focuses on several body-enabled VCO and QVCO architectures and low spur and low glitch charge pump. The dissertation will also investigate low power injection-locked frequency divider (ILFD) and phase frequency detector (PFD) based on body-enabled technique. The outcome of this research work includes innovative high performance IPs and design methodologies relevant to wireline and wireless communication systems, especially for battery powered applications.