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dc.contributor.advisorDelgado-Frias, Jose
dc.creatorVan Dyken, Jason Daniel
dc.date.accessioned2013-03-29T17:22:23Z
dc.date.available2013-03-29T17:22:23Z
dc.date.issued2012
dc.identifier.urihttp://hdl.handle.net/2376/4268
dc.descriptionThesis (Ph.D.), School of Electrical Engineering and Computer Science, Washington State Universityen_US
dc.description.abstractThis research focuses on a modular and scalable implementation of a MIPS compliant processor core for a medium-grain reconfigurable hardware. The core of this research is built upon the design of four autonomous modular functional units that provide all the operations required of a MIPS core. Four novel extremely configurable execution cores have been designed to implement a five-stage processor architecture Each of the cores can be configured for varying path widths and forwarding schemes, which have been evaluated for criteria involving area (cell count), delay, and execution efficiency. A comparative study with other reconfigurable hardware has shown the proposed cores' effective clock rate is 3% above the average for similar cores when utilizing 150nm and 90nm CMOS, and 0.99% below the average Xilinx and Altera soft processor speeds for 65nm and 45nm CMOS technologies. The proposed hardware has no specialized hardwired units such as multipliers or adders that are available in Xilinx and Altera chips. Ongoing research on FinFET technology has shown that a system clock of 5 GHz can reasonably be achieved. An analysis of the hardware has also been conducted examining issues of hardware design and the energy required for the designs to operate and how the cores would be affected if the hardware were modified. The results of this analysis have shown that module power consumption averages 0.248 mW for 8-bit and 1.855 mW for 32-bit data path widths and that the average energy required for executing a SPEC integer benchmark is 2.06 μJ. Lastly, designs for implementing a reorder buffer and reservation stations have been completed, which can be configured to track a varying number of instructions. Using these new modules with the previously analyzed components a superscalar core may be built. This core has been analyzed to determine the optimal configuration of the reorder buffer and reservation stations, and undergone the same evaluations as the five-stage cores to determine the best operation configuration and energy requirements. This analysis comparing the superscalar core with a five-stage execution core shows that a speedup of 2.073 can easily be achieved while increasing cell count by only 29%.en_US
dc.description.sponsorshipDepartment of Electrical Engineering, Washington State Universityen_US
dc.language.isoEnglish
dc.rightsIn copyright
dc.rightsPublicly accessible
dc.rightsopenAccess
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/
dc.rights.urihttp://www.ndltd.org/standards/metadata
dc.rights.urihttp://purl.org/eprint/accessRights/OpenAccess
dc.subjectComputer engineeringen_US
dc.subjectElectrical engineeringen_US
dc.subjectMedium-grain Reconfigurableen_US
dc.subjectMIPSen_US
dc.subjectPipelineen_US
dc.subjectProcessoren_US
dc.subjectSuperscalaren_US
dc.titleA MODULAR PIPELINED MEDIUM GRAIN RECONFIGURABLE PROCESSOR CORE
dc.typeElectronic Thesis or Dissertation


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