Now showing items 1-6 of 6
Design Techniques and Tradeoffs of FinFET SRAM Memories
Nine novel eight-transistor (8T) FinFET SRAM cell schemes using different shorted gate (SG) or low power (LP) FinFET configurations are studied and evaluated comprehensively in terms of leakage current, delay, read and ...
MILLIMETER-WAVE WIRELESS NETWORK-ON-CHIP: A CMOS COMPATIBLE INTERCONNECTION INFRASTRUCTURE FOR FUTURE MANY-CORE PROCESSORS
Multi-core platforms are emerging trends in the design of Systems-on-Chip (SoCs). Interconnect fabrics for these multi-core SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm ...
A MODULAR PIPELINED MEDIUM GRAIN RECONFIGURABLE PROCESSOR CORE
This research focuses on a modular and scalable implementation of a MIPS compliant processor core for a medium-grain reconfigurable hardware. The core of this research is built upon the design of four autonomous modular ...
HIGH-PERFORMANCE LOW-POWER CARBON NANOTUBE FET SRAM WITH TOLERANCE TO METALLIC CNTS
In this dissertation, an in-depth study of the design of Static Random Access Memory (SRAM) cell using Carbon Nanotube (CNT) technology is presented. Due to their superior transport properties, low voltage bias and improved ...
PERFORMANCE EVALUATION AND DESIGN TRADE-OFFS FOR WIRELESS NETWORKS ON CHIP
Massive levels of integration are making modern multi-core chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip ...
On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications
Large-scale integration of multiple cores on a single chip is the current answer to the challenge of attaining higher computation throughput while restricting power consumption within acceptable limits. Network-on-Chip ...